Fast Thermal Simulations
Recently VLSI IC design has been significantly concerned with the high temperature non-uniformity in high power chips. Non-uniformly elevated temperature limits both the performance and the reliability of packaged chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which has caused the use of conservative margins in thermal designs. The temperature non-uniformity evolves with time and so do the hot spots. These transient characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time for the chip-level thermal simulation, we have developed a matrix convolution technique, called the Power Blurring (PB) method. Our method renders the temperature profile of a packaged IC with maximum error less than 3% for all case studies done and reduces the computation time by a factor of 100 (transient case), compared to the simulations done by the industry standard tool, ANSYS.
Figure 1 Steady-state example; (a) a typical power map in VLSI ICs, (b) cross-section comparison between ANSYS and Power Blurring.
Figure 2 Transient example; (a) coarse power maps, (b) power dissipation pattern, and (c) temperature profile at the center of the IC chip.
By using an analogy with image processing and restoration, we have also developed a reverse heat dissipation solving algorithm to efficiently extract the underlying power dissipation profile from an IC temperature profile. Figure 3 shows a comparison between the real power dissipation profile behind the temperature profiles shown in Figure 1 and an estimated power dissipation profile extracted by Power Trace (PT).
Figure 3 IC power maps: (a) true (b) extracted using Power Trace algorithm